SWARization

SWAR stands for SIMD Within A Register. It is often used to refer to the implementation of SIMD style operations without specific hardware support.

For example, <32 x i4> vectors are not typically supported on most CPUs, but the operations on these vectors can usually be simulated using just a few operations on <16 x i8> vectors.

One can also consider the possibility of SWAR support for oddball vectors such as <25 x i5>, as well. However, these operations are both more complex to implement and have fewer applications.

In the Parabix framework, the following SWAR vector types are particularly important.

• 128-bit SIMD <32 x i4>, <64 x i2>, <128 x i1>
• 256-bit SIMD <64 x i4>, <128 x i2>, <256 x i1>

Pass Design

Implement support for SWAR operations through the LLVM Pass infrastructure.

• For each SWAR type supported, such as <32 x i4>, choose an implementation type, such as <16 x i8>. Replace all operations on <32 x i4> operands with equivalent logic expressed using <16 x i8> operations.