SIMD Instructions Overview

• Single-Instruction-Multiple-Data operations process multiple fields of wide-register operands using a single operational concept

• SIMD operations can be classified into some types.
  • The IDISA Project was our earlier definition of idealized SIMD operations based on this type classification.

• Vertical Operations
  • These are the most common and most representative SIMD operations.
  • For example, add two <4 x i32> vectors giving a <4 x i32> result.
  • When chaining together a series of <4 x i32> vertical operations, we say that the data values are processed in i32 lanes.
  • IDISA Vertical operations
• Horizontal Packing Operations
  • Pack fields of size fw to fw/2
  • Pack sign bits from fields together
  • IDISA Horizontal Packing operations
• Horizontal Expansion
  • Fields expand from fw to 2*fw
  • IDISA Horizontal Expansion operations
• Field movement operations.
  • shuffle the fields of SIMD vectors, while preserving the contents of the fields.
  • IDISA Field Movement operations
  • Example: SSE Shuffle Operations

Major Families of SIMD Instruction Sets

Intel/AMD x86/x86_64 Family

• MMX (64-bit), 1996
• SSE Family (128-bit wide XMM registers)
  • SSE, 1999
  • SSE2, 2001 - Integral part of the AMD64 architecture
  • SSE3, 2004
  • SSSE3, 2006
  • SSE4 (SSE4.1, SSE4.2)
• AVX Family * (256-bit wide YMM registers)
  • AVX, 2011
  • AVX2, 2013
• AVX-512 Family (512-bit ZMM registers), 2017 (Xeon-W)

• Intel Intrinsics Guide

ARM

• Neon

Power PC

• Altivec
• VMX128
• VSX

Cell Broadband Engine

• 1 Altivec PPU
• 8 extended SIMD SPU