Major Families of SIMD Instruction Sets

Intel/AMD x86/x86_64 Family

• MMX (64-bit), 1996

• SSE Family (128-bit wide XMM registers)
  • SSE, 1999
  • SSE2, 2001 - Integral part of the AMD64 architecture
  • SSE3, 2004
  • SSSE3, 2006
  • SSE4 (SSE4.1, SSE4.2)
• AVX Family * (256-bit wide YMM registers)
  • AVX, 2011
  • AVX2, 2013
• AVX-512 Family (512-bit ZMM registers), 2015+

• Intel Intrinsics Guide

ARM

• Neon

Power PC

• Altivec
• VMX128
• VSX

Cell Broadband Engine

• 1 Altivec PPU
• 8 extended SIMD SPU

Types of SIMD Instructions

• Vertical
  • SIMD operations in lanes
• Horizontal Packing
  • Pack fields of size fw to fw/2
  • Pack sign bits from fields together
• Horizontal Expansion
  • Interleave fields from two registers
• Field movement operations.
  • shuffle the fields of SIMD vectors, while preserving the contents of the fields.
  • Example: SSE Shuffle Operations